Metal oxide semiconductor (MOS) transistors have been extensively used in semiconductor integrated circuits and are well known in the electronics industry. A typical silicon MOS transistor generally comprises a polysilicon gate electrode, a gate oxide, a source and a drain. In order to improve the speed performance of MOS transistor devices, continuous efforts have been made by the industry to reduce the size of the MOS transistor devices. A reduction in device size requires a corresponding reduction in the length of the MOS transistor gate. MOS device technology has evolved in the past two decades with progressively reduced gate lengths achieved mainly by conventional device scaling methods. The feature size of a MOS transistor device has been progressively scaled down in an effort to increase the speed, performance and scale of integration.
However, conventional device scaling to reduce the gate length of a MOS transistor has its limitations. A major problem for further downward scaling of the MOS transistor gate length is the limitation of photolithographic technology. The smallest feature size of a MOS transistor gate that can be patterned by conventional photolithography is restricted by the optical phenomenon of diffraction. At the present time, ultraviolet (UV) or deep UV lights are used as light sources in photolithography processes. Because UV and deep UV lights have relatively short wavelengths, optical diffraction is reduced compared to that of visible lights, thereby enabling a photolithographic process to pattern device elements with a small feature size. However, even the photolithographic processes which utilize UV or deep UV lights are unable to effectively pattern a MOS transistor gate with a gate length of 0.1 .mu.m or less.
A further reduction in the feature size of MOS transistor devices has been attempted to overcome the limitation of optical diffraction inherent in the photolithographic process. Photoresist trimming has been attempted to achieve a small feature size beyond the limitations of photolithography. However, it is very difficult to control the shape and the size of the MOS transistor gates by using photoresist trimming.
Therefore, there is a need for a polysilicon gate fabrication process for a further reduction of the gate length beyond the limitation of photolithography. Furthermore, there is a need to be able to control the shape and the size of the polysilicon gate while reducing the size of the gate.